1. Field of the Invention
The present invention generally relates to a circuit which is immune to noise, and more particularly to an address transition detector (ATD) which includes two reset-set (RS) flip-flops for comparing a latched prior state to a new state, and included in a self-timed reset from a data output to produce an output pulse.
2. Description of the Related Art
Address transition detectors are well-known and are commonly used, for example, in static random access memories (SRAM) and erasable programmable read-only memories (EPROM). ATDs are useful for increasing the speed with which data can be read from the memory. This is accomplished by performing operations which are required for every memory read operation as soon as an address transition has been detected.
These operations include equalizing sense amplifiers and latching the previous output. The sense amplifiers are for amplifying the relatively weak signals sensed from the memory cells to be read during the read operation. Equalizing the sense amplifiers causes the amplifiers to be cleared or otherwise set up so that they are ready to process the new data to be read. Latching the previous output causes the output to stay static until the new data read from the read operation has been output from the sense amplifiers. The previous output is latched because the output of the sense amplifiers fluctuates before it finally reaches a relatively steady value. Latching the previous output ensures that the fluctuations do not pass down to the outputs.
The circuitry to equalize the sense amplifiers and latch previous outputs is well-known. Both operations are normally conducted during a memory read operation. The address transition detection circuitry permits these operations to be performed earlier than would be the case if an address transition detector was not employed. However, noise on the address lines may cause an ATD scheme to fail by beginning a read operation on an improper address.
Thus, in an attempt to solve such a problem, conventional ATDs typically employ delay elements, detect a change of a first and a second input signal, and are based on comparing a current address with a delayed address. The conventional ATD depends on comparing a new address with an address delayed through some circuitry. The circuitry may include an inverter chain and sometimes it simply depends on the natural delay of components that form a portion of the address path.
With such a structure, address inputs having "noise" (e.g., "noisy" address inputs) therewith cause difficulties with delay chains, resulting in erroneous ATD outputs. Specifically, delay paths are susceptible to noise when subjected to pulse widths narrower than the delay path itself. This is a problem. While conventional ATDs have attempted to solve such a problem by utilizing low-pass filters (LPFs) in an attempt to produce output pulses free of noise, such a structure is disadvantageous since such LPFs are relatively difficult to construct and such LPFs take up valuable real estate in the circuit.
ATD circuits based on a delay chain for an "old address" also may have problems if the address input is a pulse that is too short. With a short pulse, by the time the beginning of the pulse makes it through the delay chain the input may have already changed back to the original state, causing either no apparent transition or a shortened transition detect signal.